This invention relates generally to computer systems and more particularly to data transfer between portions of a computer system operating with different clock frequencies.
As it is known in the art, a computer system generally includes a central processing unit, a main memory, and at least one input/output (I/O) device all of which communicate together via a system bus. Generally, most central processing units transfer data and process data in a synchronous manner. That is, a synchronous central processing unit uses a clock signal as a common signal to synchronize data tranfer and processing. Generally, the input/output device such as a printer, monitor, another bus such as a network bus, or a storage device such as disk storage have a bus interface to the system bus of the CPU. Often times the interface or the peripheral device is partially or completely synchronous.
A problem often arises if the central processing unit has a clock signal which operates at a clock frequency that is different than the corresponding clock frequency of a clock signal used to operate the input/output device.
In most systems, clock signals are derived from one or more relatively stable, high frequency sources and are either provided as a train of short pulse width pulses or a train of 50% duty cycle pulses. Moreover, most systems generally use edges (either rising or falling) to trigger the clocking process.
In particular, in complex computer systems such as for example, a fault tolerant computer system, the central processing unit and associated subsystems may use a clock signal which operates at a relatively high clock frequency whereas an input/output subsystem, often containing a separate controller or central processing unit to control data transfer between the CPU of the computer and external devices, may have a clock signal which operates at a clock frequency which is substantially different from the clock frequency of the central processing unit.
A fundamental problem with transfers across a clock boundary (between two systems using different clock signals) is the need to insure that so called "set up time" (i.e. the time period that data needs to be valid and waiting at an input of a receiving device prior to arrrival of the clock signal) and "hold time" (i.e. the time period that the data needs to remain valid and at the input of the device after the clock signal has been removed are satisfied for all possible instances of data transfer. To these constraints must be added propagation delays through the sending device and uncertainity in arrival of the clocking edges of each of the clock signals. Nevertheless, data transfer between the two systems is necessary.
Several techniques have been developed in order to provide such data transfer. In one known technique, a least common multiple clock time is ascertained in accordance with the clock period of the CPU clock signal and the clock period of the input/output subsystem clock signal to provide a transfer which is predictable between the two subsystems. In this technique, corresponding periods of the clock signal frequencies are ascertained. From the periods of each clock signal a least common multiple (LCM) clock period is determined and data transfers are enabled only for that set of clock pulses corresponding to the LCM of the two clock periods. For example, if one clock has a period of 40 ns and the other a period of 60 ns, a least common multiple period would be 120 ns. Thus, data transfers could occur ever 120 ns. While slow this technique provides relatively reliable transfers. However this technique can suffer from even higher transfer latency if the LCM between the clock periods is high such as an LCM of 550 ns for clock periods of 50 ns and 55 ns.
Therefore, although this technique provides extremely predictable data transfers, a major problem with this technique is that the data transfer is retarded due to a relatively high latency between the different clock periods. This becomes particularly difficult when the so called least common multiple between the two clock periods is relatively high as in the latter example above.
To overcome this high latency problem, transfers could be attempted using faster clocks. One problem with this approach is that a race condition could develop which could make reliable transfer of data across the two systems difficult.
Deterministic data transfers although necessary for computer systems in general are particularly necessary for fault tolerant computer systems. As mentioned above, a fault tolerant computer system is used where it is important to provide a continuously operating computer environment even in the presence of a fault in the computer system to ensure that instructions are controlled and not lost and that data are not corrupted. Examples of such applications include computer processing in the financial industry and critical industrial facilities such as nuclear power plants and the like in which a failure of a computer system will cause serious disruption or catastrophic loss of data or control.
Fault tolerant computer systems have been developed to provide varying degrees of redundancy and thus provide duplicate system or system components so that data processing can continue even in the presence of some fault in within the computer system. Several approaches to provide a fault tolerant system are known in the art. One approach, is described in U.S. Pat. No. 4,907,228 by Bruckert et al. and assigned to the assignee of the present invention.
In the described fault tolerant computer system, duplicate computer systems each having a pair of central processing units operate on identical tasks. All of the computers operate on identical data in so called lock step operation. In the described computer the entire system operates at the same clock frequency for data transfers.
While the above system is acceptable, it is often desireable or necessary to interface other systems using different clock frequencies or alteratively to use faster central processing units operating at higher clock frequencies while still maintaining prior I/O systems operating with slower clocks.
In such fault tolerant computer systems therefore, it is particularly necessary to provide a predictable and deterministic data transfer between the CPU and the I/O subsystems for example. As described in the above mentioned patent, the fault tolerant computer system has two computer zones each operating on a common set of instructions and operating in synchronism. Since each of the zones further includes a pair of processors that are operating on a common set of instructions, the occurance of a fault in one of the processors in one of said zones will cause the fault tolerant computer to loose lock step operation.
When a loss in lock step operation occurs,the faulty zone is identified and replaced while the good zone continues to operate. Thus, to ensure lock step operation between the pair of rails in the zone as well as between the two zones in the fault tolerant computer, both the central processing units, as well as the I/O portions of the computer need be synchronized. Therefore, the data transfers across the zones to the I/O devices also must be performed in lock step. Therefore, data transfers must occur in a predictable and deterministic manner across clock boundaries in each of the rails of each of the zones to insure the integrity of the data transfer, as well as continued lock step operation of the fault tolerant computer.